The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs, and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, one area of manufacturing with room for improvement is wafer testing, a mechanism for determining device performance and manufacturing defects. Prior to dicing (the removal of circuit elements such as chips from a semiconductor wafer), test structures as well as functional devices on the wafer are evaluated for electrical performance. Wafer test systems typically utilize a probe card to make a secure electrical connection to the test pads on the wafer. Misalignment of the probe with the wafer test pads affects test results and can result in damage to the probe card, damage to the wafer, damage to the ICs, and lost yield. Current methods of probe alignment require an operator to visually inspect the contact between probes and pads. If the probe and wafer are not properly aligned, the probe card is removed from the wafer, adjusted, and reapplied.
Despite the qualifications of the test operators, inefficiency and the potential for error remain. Additionally, progress towards smaller devices and larger wafers may increase alignment time and lead to situations where human operators cannot visually align the components without cost-prohibitive microscopy tools. Thus while current wafer test methods have delivered positive results, they have not been entirely satisfactory in all regards. Advances in alignment mechanisms are desirable because they have the potential to improve efficiency, reduce wafer damage, and enable testing of advanced technologies.